Many of today's multilayered printed circuit boards (hereinafter also referred to as PCBs), laminate chip carriers, and the like require the formation of multiple circuits in a minimum volume or space. These structures typically comprise a stack of layers of signal, ground and/or power planes separated from each other by a layer of dielectric material. Selected ones of the conductive planes may be in electrical contact with one another, typically using plated (e.g., with copper) holes (openings) which pass through intervening dielectric layers. The plated holes are often referred to as “vias” if internally located, “blind vias” if extending a predetermined depth within the board from an external surface, or “plated thru-holes” (PTHs) if extending substantially through the board's full thickness. By the term “thru-hole” as used herein is meant to include all three types of such substrate openings.
Known methods of fabricating PCBs, chip carriers and the like typically comprise fabrication of separate inner-layer circuits (circuitized layers), which are formed by coating a photosensitive layer or film over a copper layer of a copper clad inner-layer base material. The photosensitive coating is imaged, developed and the exposed copper is etched to form conductor lines. After etching, the photosensitive film is stripped from the copper leaving the circuit pattern on the surface of the inner-layer base material. This processing is also referred to as photolithographic processing in the PCB art and further description is not deemed necessary.
After individual inner-layer circuits are formed, a multilayer stack is formed by preparing a lay-up of inner-layers, ground planes, power planes, etc., typically separated from each other by a layer of dielectric pre-preg material, the latter usually comprising a layer of glass (typically fiberglass) cloth impregnated with a partially cured material, typically a B-stage epoxy resin. Such material is also known as “FR4” material for its flame retardant (FR) rating. The top and bottom outer layers of the stack usually comprise copper clad, glass-filled, epoxy planar substrates with the copper cladding comprising exterior surfaces of the stack. The stack is laminated to form a monolithic structure using heat and pressure to fully cure the B-stage resin. The stack so formed typically has metal (usually copper) cladding on both of its exterior surfaces. Exterior circuit layers are formed in this copper cladding using procedures similar to the procedures used to form the inner-layer circuits. That is, a photosensitive film is applied to the copper cladding, exposed to patterned activating radiation and developed (removed). An etchant is then used to remove copper bared by the development of the photosensitive film. Finally, the remaining photosensitive film is removed to provide the exterior circuit layers.
Electrically conductive thru-holes (or interconnects) as described above are used to electrically connect individual circuit layers within the structure to each other and to the outer surfaces, and typically pass through all or a portion of the stack. Thru-holes are generally formed prior to the formation of circuits on the exterior surfaces by drilling holes through the stack at appropriate locations. Following several pre-treatment steps, the walls of the holes are catalyzed by contact with a plating catalyst and metallized, typically by contact with an electroless or electrolytic copper plating solution to form conductive pathways between circuit layers. Following formation of the conductive thru-holes, exterior circuits, or outer layers are formed using the procedure described above.
Chips and/or other electrical components are next mounted on one or both of the external surfaces of the multilayer structure, typically using solder mount pads and solder balls to bond the components to the PCB. The result is a substrate and component structure which may also be referred to as an electrical assembly. The components are often in electrical contact with the circuits within the structure through the conductive thru-holes, as desired. The solder pads are typically formed by coating an organic solder mask coating over the exterior circuit layers. The solder mask may be applied by screen coating a liquid solder mask coating material over the surface of the exterior circuit layers using a screen having openings defining areas where solder mount pads are to be formed. Alternatively, a photoimageable solder mask may be coated onto the board and exposed and developed to yield an array of openings defining the pads. The openings are then coated with solder using processes known to the art such as wave soldering.
The complexity of products of this type has increased significantly over the past few years. For example, PCBs for mainframe computers may have as many as thirty-six layers of circuitry or more, with the complete stack having a thickness of as much as about 0.250 inch (250 mils). These boards are typically designed with three to five mil wide signal lines and ten to twelve mil diameter thru-holes. For increased circuit densification in many of today's electronic products such as PCBs, chip carriers and the like, the industry seeks to reduce signal lines to a width of two mils or less and thru-hole diameters to two mils or less. A few of these products are available today with more in demand.
Examples of various circuitized substrates and methods of making same are further described in the documents listed below.
In U.S. Pat. No. 6,288,906, issued Sep. 11, 2001, there is described a method of making a multi-layer PCB that includes power planes for its outer conductive layers. The outer conductive layers are patterned to accept circuitry, such as integrated circuits and surface mount devices. Mounting pads are provided on the outer conductive layers which include plated-through vias (holes) for electrical interconnection with other conductive layers of the board.
In U.S. Pat. No. 6,204,453, issued Mar. 20, 2001, there is described a method of forming a PCB with a metal layer which serves as a power plane sandwiched between a pair of photo-imageable dielectric layers. Photo-formed metal filled vias and photo-formed plated through holes are in the photo-patternable material, and signal circuitry is on the surfaces of each of the dielectric materials and connected to the vias and plated through holes. A border may be around the board or card including a metal layer terminating in from the edge of one of the dielectric layers. A copper foil is provided with clearance holes. First and second layers of photo-imageable curable dielectric material are located on opposite sides of the copper. The patterns are developed on the first and second layers to reveal the metal layer through vias. At the clearance holes in the copper, through holes are developed where holes were patterned in both dielectric layers. Thereafter, the surfaces of the photo-imageable material, vias and through holes are metallized by copper plating. This is preferably done by protecting the remainder of the circuitry with photo-resist and utilizing photolithographic techniques. The photo-resist is thereafter removed, leaving a circuit board or card having metallization on both sides, vias extending from both sides to the copper layer in the center, plated through holes connecting the two outer circuitized copper layers.
In U.S. Pat. No. 5,912,809, issued Jun. 15, 1999, the electrical potentials and very high frequency (VHF) currents in a circuit board are controlled by patterning the power plane of a multiple layered, capacitive plane printed circuit board in selected geometric patterns. The selected geometric patterns, both simple and complex, control voltages and currents by channeling the capacitance capacity for usage directed to a particular integrated circuit or circuits, isolated to a particular integrated circuit or circuits, or shared between integrated circuits.
In U.S. Pat. No. 5,822,856, issued Oct. 28, 1998, there is described a process wherein circuit boards are manufactured by forming a substrate with a dielectric surface, laminating a metal foil and a peelable film to the substrate, and forming holes in the substrate through the peelable film and foil. A filler material with an organic base may be filled with electroconductive particles or dielectric thermoconductive particles. The filler material is laminated onto the peelable film with sufficient heat and pressure to force the filler material to fill the holes. For thermoconductive filler, the holes are filled sufficient for electrical connection through the holes. The filler material is abraded to the level of the foil and is then copper plated. The copper is patterned to form a wiring layer. A permanent dielectric photoresist layer is formed over the wiring layer, and via holes are formed through the photoimageable dielectric over pads and conductors of the wiring layer. Holes are formed through the substrate and the photoimageable dielectric, walls of the via holes, and walls of the through holes are copper plated. The copper plating on the photoimageable dielectric is patterned of form an exterior wiring layer. Components and/or pins are attached to the surface of the circuitized substrate with solder joints to form a high density circuit board assembly.
In U.S. Pat. No. 5,685,070, issued Nov. 11, 1997, there is described a method of making a printed circuit board or card for direct chip attachment that includes at least one power core, at least one signal plane that is adjacent the power core, and plated thru-holes for electrical connection is provided. In addition, a layer of dielectric material is adjacent the power core and a circuitized conductive layer is adjacent the dielectric material, followed by a layer of photosensitive dielectric material adjacent the conductive layer. Photodeveloped blind vias for subsequent connection to the power core and drilled blind vias for subsequent connection to the signal plane are provided.
In U.S. Pat. No. 5,448,020, issued Sep. 5, 1995, there is described a system and method for providing a controlled impedance flex circuit which includes providing an insulative flexible substrate having opposed first and second surfaces and having through holes extending from the first surface to the second surface. A pattern of conductive traces is formed on the first surface of the flexible substrate. A film of conductive adhesive is applied to the second surface and to the through holes. The through holes are aligned to contact ground traces in the pattern of conductive traces on the first surface. Thus, a ground plane is established for creating an environment for high frequency signal propagation. The conductive adhesive may be a b-stage epoxy or a thermoplastic material. In the preferred embodiment, a tape automated bonding frame is fabricated.
In U.S. Pat. No. 5,418,689, issued May 23, 1995, there is described a method of making a printed circuit board for direct chip attachment that includes at least one power core, at least one signal plane adjacent the power core, and plated thru-holes for electrical connection. In addition, a layer of dielectric material is adjacent the power core and a circuitized conductive layer is adjacent the dielectric material, followed by a layer of photosensitive dielectric material adjacent the conductive layer.
In U.S. Pat. No. 5,384,433, issued Jan. 24, 1995, there is described a method of making a PCB that includes an array of conductive pads including component-mounting holes disposed on first and second surfaces thereon. An array of conductive attachment lands arranged in pairs of first and second attachment lands are disposed on the first and second surfaces. The first and second attachment lands are insulated from one another and separated by a distance selected to allow attachment of standard sized components therebetween on the first and second surfaces of said circuit board. First and second conductive power distribution planes are disposed on the first and second surfaces and are insulated from the conductive pads and the second attachment lands disposed thereon.
In U.S. Pat No. 5,334,487, issued Aug. 2, 1994, there is described a method of forming a pattern of conductive material on dielectric material with access openings or vias through said dielectric material and such a structure. A sheet of conductive material, which is to be circuitized, is provided with a layer of a first photo-imageable dielectric material on one face thereof. A layer of a second photo-imageable material, such as a conventional photo-resist material, is provided on the opposite face of the conductive material. The layer of said first photo-imageable material is selected such that it will not be developed by the developer that develops the layer of said second material. The two layers of photo-imageable material are pattern-wise exposed to radiation. The second layer of material is developed and the revealed underlying conductive material is etched to form the desired circuit pattern. The first layer is then developed to form openings or vias communicating with the circuit pattern, and these are then filled with a conductive material such as solder.
In U.S. Pat. No. 5,229,550, issued Jul. 20, 1993, there is described a structure and method for making a high density circuit board. Using photosensitive or other dielectric materials over a circuitized power core, vias and lands are opened up, filled with joining metal and aligned with the next level, eliminating a major registration problem in building up a high density composite and reducing the number of steps in the manufacturing process.
As described herein, the present invention represents a significant improvement over known processes, including those described above, used in the production of multilayered circuitized substrates such as PCBs. One particularly significant feature of this invention is the use of two facing sub-composites which, when bonded together, form a common conductive layer with filled (with dielectric material) openings therein. These filled openings may then be drilled out and formed into conductive openings. Other highly advantageous features of this invention are discernible from the following description.
It is believed that such an invention will represent a significant advancement in the art.